Generally, when a source/drain region of a complementary metal oxide semiconductor (CMOS) transistor is formed through an epitaxial process, a single layer of a material (usually including a dopant) is formed. Such a layer may be a single layer of silicon with a dopant such as phosphorous. One method of forming this single layer uses a selective deposition process that utilizes a precursor such as dichlorosilane (DCS) along with an etchant such as hydrochloric acid in order to selectively grow a layer of epitaxial silicon on a base of underlying silicon material. This type of formation process forms a low activation, high diffusibility layer, in which the dopants can easily diffuse out of the epitaxial layer with a low temperature of anneal. However, by forming such a low activation, high diffusibility single layer, diffusion from such a layer cannot be well controlled, leading to concerns regarding short channel effects in devices formed from such a process.
In order to address these concerns, another process has been attempted by which a high activation and low diffusibility single layer has been formed. In such a process a precursor such as Si2H6 or Si3H8 is utilized to form both a layer of epitaxial silicon over an underlying silicon layer along with a layer of polysilicon over non-silicon layers. After such a growth and deposition, the unit may be purged of precursors and a selective etching of the polysilicon (using etchants such as HCl along with a catalyst like of GeH4) may be initiated in order to remove, the polysilicon without removing the epitaxially grown silicon (or partially removing the epitaxially grown silicon). This deposition and selective etching may be repeated a number of times in a cyclical fashion in order to grow the desired epitaxial silicon layer to the desired thickness.
However, this cyclical process also has its drawbacks. In particular, this process forms a high activation and low diffusibility single layer that leads to an increase of the resistance within the LDD region of transistors. Additionally, the use of this cyclical process can lead to the formation of voids underneath spacers that may be used with the gate stack. As such, this cyclical process forms a high activation, low diffusibility single layer that has its own problems to replace the problems with which it helps.